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December 2006
HYS72T512341HHP-[3.7/5]-B HYS72T512341HJP-[3.7/5]-B HYS72T512341HKP-[3.7/5]-B
240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RoHs Compliant Products
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-[3.7/5]-B, HYS72T512341HJP-[3.7/5]-B, HYS72T512341HKP-[3.7/5]-B Revision History: 2006-12, Rev. 1.0 Page All All All Chapter 4 Subjects (major changes since last revision) Qimonda update Adapted internet edition Added HYS672T512341HJP-[3.7/5]-B and HYS72T512341HKP-[3.7/5]-B modules SPD codes updated
Previous Revision: 2006-07, Rev. 0.5
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 11032006-VX0M-M6IH
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
Features
* * * * * * * * * Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM RDIMM Dimensions (nominal): 18,30 mm high, 133.35 mm wide All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications. RoHS compliant products1)
* 240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules. * Four rank 512M x72 module organization, and 512M x4 chip organization * Registered DIMM Parity bit for address and control bus * 4 GB module built with 512 Mbit DDR2 SDRAMs in SGA4FBGA-60 and PG-A4FBGA-60 chipsize packages. * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * Programmable CAS Latencies (3, 4, 5), Burst Length (4 & 8) and Burst Type * Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3.7 PC2-4200 4-4-4 -5 PC2-3200 3-3-3 200 200 200 15 15 40 55 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
1.2
Description
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-ball I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The Qimonda HYS72T512341H[H/J/K]P-[3.7/5]-B module family are Very Low Profile Registered DIMM (with parity) modules with 18,3 mm height based on DDR2 technology. DIMMs are available as ECC modules in 512M x72 (4 GB) organization and density, intended for mounting into 240-Ball connector sockets. The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type PC2-4200 HYS72T512341HHP-3.7-B HYS72T512341HJP-3.7-B HYS72T512341HKP-3.7-B PC2-3200 HYS72T512341HHP-5-B HYS72T512341HJP-5-B HYS72T512341HKP-5-B 4 GB 4Rx4 PC2-3200P-333-12-ZZ 4 GB 4Rx4 PC2-3200P-333-12-ZZ 4 GB 4Rx4 PC2-3200P-333-12-ZZ 4 Rank ECC 4 Rank ECC 4 Rank ECC 4 GB (x4) 4 GB (x4) 4 GB (x4) 4 GB 4Rx4 PC2-4200P-444-12-ZZ 4 GB 4Rx4 PC2-4200P-444-12-ZZ 4 GB 4Rx4 PC2-4200P-444-12-ZZ 4 Rank ECC 4 Rank ECC 4 Rank ECC 4 GB (x4) 4 GB (x4) 4 GB (x4)
1)
Compliance Code
2)
Description
SDRAM Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T512341HJP-3.7-B, indicating Rev. "B" dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200P-444-12", where 4200P means Registered DIMM modules (Parity bit) with 4.26 GB/sec Module Bandwidth and "444-12" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2.
TABLE 3
Address Format
DIMM Density Module Organization 4 GB 512M x72 Memory Ranks 4 ECC/ Non-ECC ECC # of SDRAMs 18 x4 # of row/bank/column bits 14/2/11
TABLE 4
Components on Modules
Product Type HYS72T512341HHP HYS72T512341HJP HYS72T512341HKP
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
DRAM Components HYB18T2G401BHF
DRAM Density 512 Mbit
DRAM Organisation 512M x4
Note
1)
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HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
2
2.1
Pin Configuration
Pin Configuration
and Table 7 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6
TABLE 5
Pin Configuration of RDIMM
Pin No. Clock Signals 185 186 52 171 CK0 CK0 CKE0 CKE1 NC Control Signals 193 76 220 221 192 74 73 18 Address Signals 71 190 54 BA0 BA1 BA2 NC I I I I SSTL SSTL SSTL SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS Not Connected Less than 1Gb DDR2 SDRAMS Bank Address Bus 1:0 S0 S1 S2 S3 RAS CAS WE RESET I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS Register Reset Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Chip Select Rank 3:0 I I I I NC SSTL SSTL SSTL SSTL -- Clock Enables 1:0 Note: 2-Ranks module Not Connected Note: 1-Rank module Clock Signal CK0, Complementary Clock Signal CK0 Name Pin Type Buffer Type Function
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Pin No. 188 183 63 182 61 60 180 58 179 177 70 57 176 196
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC
Pin Type I I I I I I I I I I I I I I I NC I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address Bus 12:0, Address Signal 10/AutoPrecharge
Address Signal 13 Not Connected Note: Non CA parity modules based on 256 Mbit component Not Connected Not Connected Data Bus 63:0 Data Input/Output pins
174 173 Data Signals 3 4 9 10 122 123 128 129 12 13
A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
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HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Pin No. 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 206 89 90 95 96 208 209 214 215 98 99
Name DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0 Data Input/Output pins
Data Bus 63:0
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Pin No. 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Check Bits 42 43 48 49 161 162 167 168 Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113
Name DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
Check Bits 7:0 Check Bit Input / Output pins
Data Strobes 17:0
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HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Pin No. 46 45 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165 Data Mask 125 134 146 155 202 211 223 232 164 EEPROM 120 119 239 240 101 Parity 55
Name DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 SCL SDA SA0 SA1 SA2 ERR_OUT PAR_IN
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I/O I I I O I
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS OD CMOS CMOS CMOS CMOS CMOS
Function Data Strobes 17:0
Data Masks 8:0 Note: x8 based module
Serial Bus Clock Serial Bus Data Serial Address Select Bus 2:0
Parity bits
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Pin No. Power Supplies 1 238 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197
Name
Pin Type AI PWR PWR
Buffer Type -- -- --
Function
VREF VDDSPD VDDQ
I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply
VDD
PWR
--
Power Supply
2, 5, 8, 11, 14, 17, VSS 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 Other Pins 19, 55, 68, 102, 137, 138, 173 195 77 NC ODT0 ODT1 NC
GND
--
Ground Plane
NC I I NC
-- SSTL SSTL --
Not connected On-Die Termination Control 1:0 Note: 2-Ranks module Note: 1-Rank modules
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TABLE 6
Abbreviations for Buffer Type
Abbreviation SSTL CMOS OD Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NU NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected
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HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for RDIMM (240 pins)
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3
3.1
Electrical Characteristics
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
VDD VDDQ VDDL VIN, VOUT TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS
-1.0 -0.5 -0.5 -0.5
V V V V C
1) 1)2) 1)2) 1) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 90 C
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 90 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 80 C to 90 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
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3.2
D.C. Characteristics
TABLE 10
Operating Conditions
Parameter
Symbol
Values Min. Max. +65 +90 +100 +105 90
Unit
Note
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
1) 2) 3) 4)
TOPR TCASE TSTG
PBar
0 0 - 50 +69 10
C C C kPa %
5) 1)2)3)4)
HOPR
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 80 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%. 5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Typ. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V
3) 1) 2)
Unit
Note
In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
- 0.30
VDDQ + 0.3 VREF - 0.125
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3.3
AC Characteristics
TABLE 12
Speed Grade Definition Speed Bins for DDR2-533C and DDR2-400B
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns).
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol
DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- --
DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- --
Unit
Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions. * Table 13 "IDD Measurement Conditions" on Page 16 * Table 14 "Definitions for IDD" on Page 17 * Table 15 "IDD Specification for HYS72T512341H[HJ/K]P-[3.7/5]-B" on Page 18
TABLE 13
IDD Measurement Conditions
Parameter Symbol Note
1)2)3)4)5)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current - Burst Read IDD4R All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX; tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
6)
IDD4W
IDD5B
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Parameter Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Symbol Note
1)2)3)4)5)
IDD5D
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 14 4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6)
5) For details and notes see the relevant Qimonda component data sheet 6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 14
Definitions for IDD
Parameter LOW STABLE FLOATING SWITCHING Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
Inputs are stable at a HIGH or LOW level Inputs are VREF = VDDQ /2 Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes
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TABLE 15
IDD Specification for HYS72T512341H[HJ/K]P-[3.7/5]-B
Product Type Organization HYS72T512341H[H/J/K]P-3.7-B 4 GB 4 Ranks x72 -3.7 Symbol Max. 2780 2960 3970 1730 3750 4330 3250 1880 3590 3590 3950 1880 360 4220 HYS72T512341H[HJ/K]P-5-B 4 GB 4 Ranks x72 -5 Max. 2450 2610 3420 1480 3280 3780 2700 1620 3060 3060 3600 1620 504 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3)4) 3)5) 2) 2) 2) 3)6) 3)6) 2)
Unit
Note1)
3890 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode
4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0C TCase 85C
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 16 "SPD Codes for PC2-4200P-444" on Page 19 * Table 17 "SPD Codes for PC2-3200P-333" on Page 24
TABLE 16
SPD Codes for PC2-4200P-444
HYS72T512341HHP-3.7-B HYS72T512341HJP-3.7-B Product Type HYS72T512341HKP-3.7-B 4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 80 08 08 0E 0B 03 48 00 05 3D 50 06 81 04
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 80 08 08 0E 0B 03 48 00 05 3D 50 06 81 04
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200P-444 Rev. 1.2 HEX 80 08 08 0E 0B 03 48 00 05 3D 50 06 81 04
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-3.7-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 04 00 0C 04 38 01 01 05 07 3D 50 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00
HYS72T512341HJP-3.7-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 04 00 0C 04 38 01 01 05 07 3D 50 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00
Label Code JEDEC SPD Revision Byte# 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Description Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
PC2-4200P-444 Rev. 1.2 HEX 04 00 0C 04 38 01 01 05 07 3D 50 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
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HYS72T512341HKP-3.7-B
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-3.7-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 00 3C 69 80 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 9F 7F 7F
HYS72T512341HJP-3.7-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 00 3C 69 80 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 9F 7F 7F
Label Code JEDEC SPD Revision Byte# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Description
PC2-4200P-444 Rev. 1.2 HEX 00 3C 69 80 1E 28 0F 50 7A 43 29 36 21 41 2A 40 1E 22 C4 8C 61 78 12 9F 7F 7F
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2)
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HYS72T512341HKP-3.7-B
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-3.7-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 7F 7F 7F 51 00 00 xx 37 32 54 35 31 32 33 34 31 48 4A 50 33 2E 37 42 20 20 0x
HYS72T512341HJP-3.7-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX 7F 7F 7F 51 00 00 xx 37 32 54 35 31 32 33 34 31 48 4B 50 33 2E 37 42 20 20 0x
Label Code JEDEC SPD Revision Byte# 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Description Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code
PC2-4200P-444 Rev. 1.2 HEX 7F 7F 7F 51 00 00 xx 37 32 54 35 31 32 33 34 31 48 48 50 33 2E 37 42 20 20 2x
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HYS72T512341HKP-3.7-B
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-3.7-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX xx xx xx xx 00 FF
HYS72T512341HJP-3.7-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-4200P-444 Rev. 1.2 HEX xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 92 93 94 95 - 98 128 255 Description Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2-4200P-444 Rev. 1.2 HEX xx xx xx xx 00 FF
99 - 127 Not used
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HYS72T512341HKP-3.7-B
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
TABLE 17
SPD Codes for PC2-3200P-333
HYS72T512341HHP-5-B HYS72T512341HJP-5-B Product Type HYS72T512341HKP-5-B 4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 80 08 08 0E 0B 03 48 00 05 50 60 06 81 04 04 00 0C 04 38 01 01 05 07 50
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 80 08 08 0E 0B 03 48 00 05 50 60 06 81 04 04 00 0C 04 38 01 01 05 07 50
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-3200P-333 Rev. 1.2 HEX 80 08 08 0E 0B 03 48 00 05 50 60 06 81 04 04 00 0C 04 38 01 01 05 07 50
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns]
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-5-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 60 50 60 3C 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B
HYS72T512341HJP-5-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 60 50 60 3C 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B
Label Code JEDEC SPD Revision Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Description
PC2-3200P-333 Rev. 1.2 HEX 60 50 60 3C 1E 3C 28 01 35 47 15 27 3C 28 1E 00 00 37 69 80 23 2D 0F 50 7A 3B
tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0)
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HYS72T512341HKP-5-B
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-5-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 25 36 1E 38 2A 38 1D 21 C4 8C 59 5C 12 D3 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54
HYS72T512341HJP-5-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 25 36 1E 38 2A 38 1D 21 C4 8C 59 5C 12 D3 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54
Label Code JEDEC SPD Revision Byte# 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Description T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3
PC2-3200P-333 Rev. 1.2 HEX 25 36 1E 38 2A 38 1D 21 C4 8C 59 5C 12 D3 7F 7F 7F 7F 7F 51 00 00 xx 37 32 54
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HYS72T512341HKP-5-B
Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
HYS72T512341HHP-5-B
Organization
4 GByte x72 4 Ranks (x4)
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 35 31 32 33 34 31 48 4A 50 35 42 20 20 20 20 0x xx xx xx xx 00 FF
HYS72T512341HJP-5-B
Product Type
4 GByte x72 4 Ranks (x4) PC2-3200P-333 Rev. 1.2 HEX 35 31 32 33 34 31 48 4B 50 35 42 20 20 20 20 0x xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 128 255 Description Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2-3200P-333 Rev. 1.2 HEX 35 31 32 33 34 31 48 48 50 35 42 20 20 20 20 2x xx xx xx xx 00 FF
99 - 127 Not used
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
5
Package Outlines
FIGURE 2
Package Outline L-DIM-240-55
In this chapter the Package Outline L-DIM-240-55 is included.
Notes 1. 2. 3. 4. Drawing according to ISO 8015 Dimensions in mm General tolerances +/- 0.15 Heat sink is not included in the drawing. Additional width might be required.
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 19 and for components in Table 20.
Qimonda's nomenclature uses simple coding combined with some propriatory coding. Table 18 provides examples for module and component product type number as well as the
TABLE 18
Nomenclature Fields and Examples
Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 4 64/128 5 0 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
512/1G 16
TABLE 19
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Field 10
Description Speed Grade
Values -2.5F -2.5 -3 -3S -3.7 -5
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
11
Die Revision
-A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 20
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
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Internet Data Sheet
HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules
Table of Contents
1 1.1 1.2 2 2.1 3 3.1 3.2 3.3 3.4 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 16
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Internet Data Sheet
Edition 2006-12 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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